AVR Microcontroller Interrupts

In order for the microcontroller to respond to an interrupt event the interrupt feature of the microcontroller must be enabled along with the specific interrupt. This is done by setting the Global Interrupt Enabled bit and the Interrupt Enable bit of the specific interrupt.

Interrupt Service Routine or Interrupt Handler
An Interrupt Service Routine (ISR) or Interrupt Handler is a piece of code that should be execute when an interrupt is triggered. Usually each enabled interrupt has its own ISR. In AVR assembly language each ISR MUST end with the RETI instruction which indicates the end of the ISR.

Interrupt Flags and Enabled bits
Each interrupt is associated with two (2) bits, an Interrupt Flag Bit and an Interrupt Enabled Bit. These bits are located in the I/O registers associated with the specific interrupt:

• The interrupt flag bit is set whenever the interrupt event occur, whether or not the interrupt is enabled.
• The interrupt enabled bit is used to enable or disable a specific interrupt. Basically is tells the microcontroller whether or not it should respond to the interrupt if it is triggered.

In summary basically both the Interrupt Flag and the Interrupt Enabled are required for an interrupt request to be generated as shown in the figure below.

Global Interrupt Enabled Bit
Apart from the enabled bits for the specific interrupts the global interrupt enabled bit MUST be enabled for interrupts to be activated in the microcontoller.

For the AVR 8-bits microcontroller this bit is located in the Status I/O Register (SREG). The Global Interrupt Enabled is bit 7, the I bit, in the SREG.

1. The RESET interrupt - Triggered from pin 9.
2. External Interrupt 0 (INT0) - Triggered from pin 16.
3. External Interrupt 1 (INT1) - Triggered from pin 17.
4. External Interrupt 2 (INT2) - Triggered from pin 3.

Very Important
When writing assembly codes for your AVR microcontroller utilizing the interrupt feature the following MUST be observed:

• The interrupt MUST be enabled by setting its enabled bit in the appropriate I/O register.
• The Global Interrupt bit, the I bit, in the microcontroller's status register (SREG) MUST also be enabled.
• The stack MUST be initialized. When an interrupt is being service the microcontroller need to store critical information on the stack and so it must be initialized.
• The Interrupt Service Routine (ISR) MUST end with the RETI instruction, which indicates the end of the ISR. The microcontroller needs to know when it reaches the end of the ISR so it can return to its previous task.

1. The microcontroller completes the execution of the current instruction, clears the I bit and stores the address of the next instruction that should have been executed (the content of the PC) on the stack.
2. The interrupt vector of the triggered interrupt is then loaded in the PC and the microcontroller starts execution from that point up until is reaches a RETI instruction.
3. Upon the the execution of the RETI instruction the address that was stored on the stack in step 1 is reloaded in the PC and the I bit is re-enabled.
4. The microcontroller then start executing instructions from that point. That is the point that it left off when the interrupt was triggered.

Important Notes:
As it relates to AVR microcontrollers - An interrupt vector is the memory address of an interrupt handler. The interrupt vector for each interrupt provided by the AVR microcontrollers can be found in its datasheet. The table below is an extract from the interrupt section of the ATMega8515 datasheet and gives the interrupt vectors for the interrupts provided with this microcontroller.

Please note here that the interrupt vectors are apart of the microcontroller's program memory. As such when utilizing interrupts this section of memory should be reserved to store pointers to interrupt handlers and not to store regular programs. For the ATMega8515 microcontroller to ensure that regular programs are not stored in this section of program memory insert the following line is your AVR assembly code.

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